drivers/clocksource/sh_cmt.c:719

Table of Contents

1 sh_cmt users and clock trees

1.1 platform_device sh-cmt-16

1.1.1 arch/sh/kernel/cpu/sh2/setup-sh7619.c

  1. Clock tree

    Initialized through arch_clk_init(), cpg_clk_init().

    Device relevant input clock
    sh-cmt-16.0 peripheral_clk
    peripheral_clk master_clk
    master_clk  

    Likewise for sh-cmt-32.0.

1.1.2 arch/sh/kernel/cpu/sh2a/setup-sh7203.c

Instantiations of cmt_device:

Used by SH_RSK7203 board.

  1. Clock tree

    Initialized through arch_clk_init(), cpg_clk_init(). C.f. CPG clock tree.

1.1.3 arch/sh/kernel/cpu/sh2a/setup-sh7206.c

  1. Clock tree

    Initialized through arch_clk_init(), cpg_clk_init(). C.f. CPG clock tree.

1.1.4 arch/sh/kernel/cpu/sh2a/setup-sh7264.c

Instantiations of cmt_device:

Used by SH_RSK7264 board.

  1. Clock tree

    Initialized through arch_clk_init().

    Device relevant input clock
    sh-cmt-16.0 &mstp_clks[MSTP72]
    mstp_clks &div4_clks[DIV4_P]
    div4_clks &pll_clk
    pll_clk &extal_clk
    extal_clk  

1.1.5 arch/sh/kernel/cpu/sh2a/setup-sh7269.c

Instantiations of cmt_device:

Used by SH_RSK7269 board.

  1. Clock tree

    Initialized through arch_clk_init().

    Device relevant input clock
    sh-cmt-16.0 &mstp_clks[MSTP72]
    mstp_clks &peripheral0_clk
    peripheral0_clk &pll_clk
    pll_clk &extal_clk
    extal_clk  

1.2 platform_device sh-cmt-32

1.2.1 arch/sh/kernel/cpu/sh3/setup-sh7720.c

  1. Clock tree

    Initialized through arch_clk_init(), cpg_clk_init(). C.f. CPG clock tree.

1.2.2 arch/sh/kernel/cpu/sh4a/setup-sh7722.c

  1. Clock tree

    Initialized through arch_clk_init().

    Device relevant input clock
    sh-cmt-32.0 &mstp_clks[HWBLK_CMT]
    mstp_clks &r_clk
    r_clk  

1.2.3 arch/sh/kernel/cpu/sh4a/setup-sh7723.c

Instantiations of cmt_device:

Used by SH_AP325RXA board.

  1. Clock tree

    Initialized through arch_clk_init().

    Device relevant input clock
    sh-cmt-32.0 &mstp_clks[HWBLK_CMT]
    mstp_clks &r_clk
    r_clk  

1.2.4 arch/sh/kernel/cpu/sh4a/setup-sh7724.c

  1. Clock tree

    Initialized through arch_clk_init().

    Device relevant input clock
    sh-cmt-32.0 &mstp_clks[HWBLK_CMT]
    mstp_clks &r_clk
    r_clk  

1.2.5 arch/sh/kernel/cpu/sh4a/setup-sh7343.c

  1. Clock tree

    Initialized through arch_clk_init().

    Device relevant input clock
    sh-cmt-32.0 &mstp_clks[MSTP014]
    mstp_clks &r_clk
    r_clk  

1.2.6 arch/sh/kernel/cpu/sh4a/setup-sh7366.c

Instantiations of cmt_device:

Not used by any board?

  1. Clock tree

    Initialized through arch_clk_init().

    Device relevant input clock
    sh-cmt-32.0 &mstp_clks[MSTP014]
    mstp_clks &r_clk
    r_clk  

1.3 Device tree nodes with compatible=renesas,cmt-32*

None.

1.4 Device tree nodes with compatible=renesas,cmt-48*

1.4.1 arch/arm/boot/dts/r8a73a4.dtsi

Included from arch/arm/boot/dts/r8a73a4-ape6evm.dts:12. Board has no ->init_time, the of_clk_init() path in arm's time_init() is taken.

  1. Clock tree
    Node compatible relevant input clock
    cmt1 renesas,cmt-48-r8a73a4, renesas,cmt-48-gen2 <&mstp3_clks R8A73A4_CLK_CMT1>
    mstp3_clks renesas,r8a73a4-mstp-clocks, renesas,cpg-mstp-clocks <&extalr_clk>
    extalr_clk fixed-clock

1.4.2 arch/arm/boot/dts/r8a7740.dtsi

Included from arch/arm/boot/dts/r8a7740-armadillo800eva.dts:12. Board has no ->init_time, the of_clk_init() path in arm's time_init() is taken.

  1. Clock tree
    Node compatible relevant input clock
    cmt1 renesas,cmt-48-r8a7740, renesas,cmt-48 <&mstp3_clks R8A7740_CLK_CMT1>
    mstp3_clks renesas,r8a7740-mstp-clocks, renesas,cpg-mstp-clocks <&cpg_clocks R8A7740_CLK_R>
    cpg_clocks renesas,r8a7740-cpg-clocks <&extal1_clk>
    extal1_clk fixed-clock  

1.4.3 arch/arm/boot/dts/r8a7790.dtsi

  1. Clock tree
    Node compatible relevant input clock
    cmt0 renesas,cmt-48-r8a7790, renesas,cmt-48-gen2 <&mstp1_clks R8A7790_CLK_CMT0>
    mstp1_clks renesas,r8a7790-mstp-clocks, renesas,cpg-mstp-clocks <&rclk_clk>
    rclk_clk fixed-factor-clock <&cpg_clocks R8A7790_CLK_PLL1>
    cpg_clocks renesas,r8a7790-cpg-clocks, renesas,rcar-gen2-cpg-clocks <&extal_clk>
    extal_clk fixed-clock  
    Node compatible relevant input clock
    cmt1 renesas,cmt-48-r8a7790, renesas,cmt-48-gen2 <&mstp3_clks R8A7790_CLK_CMT1>
    mstp3_clks renesas,r8a7790-mstp-clocks, renesas,cpg-mstp-clocks <&rclk_clk>
    rclk_clk fixed-factor-clock <&cpg_clocks R8A7790_CLK_PLL1>
    cpg_clocks renesas,r8a7790-cpg-clocks, renesas,rcar-gen2-cpg-clocks <&extal_clk>
    extal_clk fixed-clock  

1.4.4 arch/arm/boot/dts/r8a7791.dtsi

  1. Clock tree
    Node compatible relevant input clock
    cmt0 renesas,cmt-48-r8a7791, renesas,cmt-48-gen2 <&mstp1_clks R8A7791_CLK_CMT0>
    mstp1_clks renesas,r8a7791-mstp-clocks, renesas,cpg-mstp-clocks <&rclk_clk>
    rclk_clk fixed-factor-clock <&cpg_clocks R8A7791_CLK_PLL1>
    cpg_clocks renesas,r8a7791-cpg-clocks, renesas,rcar-gen2-cpg-clocks <&extal_clk>
    extal_clk fixed-clock  
    Node compatible relevant input clock
    cmt1 renesas,cmt-48-r8a7791, renesas,cmt-48-gen2 <&mstp3_clks R8A7791_CLK_CMT1>
    mstp3_clks renesas,r8a7791-mstp-clocks, renesas,cpg-mstp-clocks <&rclk_clk>
    rclk_clk fixed-factor-clock <&cpg_clocks R8A7791_CLK_PLL1>
    cpg_clocks renesas,r8a7791-cpg-clocks, renesas,rcar-gen2-cpg-clocks <&extal_clk>
    extal_clk fixed-clock  

1.4.5 arch/arm/boot/dts/r8a7793.dtsi

  1. Clock tree
    Node compatible relevant input clock
    cmt0 renesas,cmt-48-r8a7793, renesas,cmt-48-gen2 <&mstp1_clks R8A7793_CLK_CMT0>
    mstp1_clks renesas,r8a7793-mstp-clocks, renesas,cpg-mstp-clocks <&rclk_clk>
    rclk_clk fixed-factor-clock <&cpg_clocks R8A7793_CLK_PLL1>
    cpg_clocks renesas,r8a7793-cpg-clocks, renesas,rcar-gen2-cpg-clocks <&extal_clk>
    extal_clk fixed-clock  
    Node compatible relevant input clock
    cmt1 renesas,cmt-48-r8a7793, renesas,cmt-48-gen2 <&mstp3_clks R8A7793_CLK_CMT1>
    mstp3_clks renesas,r8a7793-mstp-clocks, renesas,cpg-mstp-clocks <&rclk_clk>
    rclk_clk fixed-factor-clock <&cpg_clocks R8A7793_CLK_PLL1>
    cpg_clocks renesas,r8a7793-cpg-clocks, renesas,rcar-gen2-cpg-clocks <&extal_clk>
    extal_clk fixed-clock  

1.4.6 arch/arm/boot/dts/r8a7794.dtsi

  1. Clock tree
    Node compatible relevant input clock
    cmt0 renesas,cmt-48-gen2 <&mstp1_clks R8A7794_CLK_CMT0>
    mstp1_clks renesas,r8a7794-mstp-clocks, renesas,cpg-mstp-clocks <&rclk_clk>
    rclk_clk fixed-factor-clock <&cpg_clocks R8A7794_CLK_PLL1>
    cpg_clocks renesas,r8a7794-cpg-clocks, renesas,rcar-gen2-cpg-clocks <&extal_clk>
    extal_clk fixed-clock  
    Node compatible relevant input clock
    cmt1 renesas,cmt-48-gen2 <&mstp3_clks R8A7794_CLK_CMT1>
    mstp3_clks renesas,r8a7794-mstp-clocks, renesas,cpg-mstp-clocks <&rclk_clk>
    rclk_clk fixed-factor-clock <&cpg_clocks R8A7794_CLK_PLL1>
    cpg_clocks renesas,r8a7794-cpg-clocks, renesas,rcar-gen2-cpg-clocks <&extal_clk>
    extal_clk fixed-clock  

1.4.7 arch/arm/boot/dts/sh73a0.dtsi

Included from arch/arm/boot/dts/sh73a0-kzm9g.dts:15 Board has no ->init_time, the of_clk_init() path in arm's time_init() is taken.

  1. Clock tree
    Node compatible relevant input clock
    cmt1 renesas,cmt-48-sh73a0, renesas,cmt-48 <&mstp3_clks SH73A0_CLK_CMT1>
    mstp3_clks renesas,sh73a0-mstp-clocks, renesas,cpg-mstp-clocks <&extalr_clk>
    extalr_clk fixed-clock  

2 Clock rate/parent changers in arch/arm and arch/sh

git grep -n 'clk_set_\(rate\|parent\)' -- arch/arm arch/sh

Manually cleaned up.

2.1 arch/arm

2.1.1 arch/arm/mach-davinci/

ARCH_DAVINCI boards do not use sh_cmt.

  1. arch/arm/mach-davinci/clock.c:594
    clk_set_rate(refclk, rate);
    
  2. arch/arm/mach-davinci/da850.c:1202
    return clk_set_rate(pllclk, index);
    

2.1.2 arch/arm/mach-mvebu/platsmp.c:68

clk_set_rate(cpu_clk, rate);

ARCH_MVEBU boards do not use sh_cmt.

2.1.3 arch/arm/mach-omap1/

ARCH_OMAP1 boards do not use sh_cmt.

  1. arch/arm/mach-omap1/clock.c:696
    ret = omap1_clk_set_rate(clk, rate);
    
  2. arch/arm/mach-omap1/serial.c:149
    clk_set_rate(uart1_ck, 12000000);
    
  3. arch/arm/mach-omap1/serial.c:159
    clk_set_rate(uart2_ck, 12000000);
    
  4. arch/arm/mach-omap1/serial.c:161
    clk_set_rate(uart2_ck, 48000000);
    
  5. arch/arm/mach-omap1/serial.c:171
    clk_set_rate(uart3_ck, 12000000);
    

2.1.4 arch/arm/mach-omap2/

ARCH_OMAP2PLUS boards do not use sh_cmt.

  1. arch/arm/mach-omap2/io.c:399
    v = clk_set_rate(dpll3_m2_ck, rate);
    
  2. arch/arm/mach-omap2/omap2-restart.c:39
    clk_set_rate(reset_virt_prcm_set_ck, rate);
    

2.1.5 arch/arm/mach-s3c24xx/cpufreq-utils.c:65

clk_set_rate(cfg->mpll, cfg->pll.frequency);

ARCH_S3C24XX boards do not use sh_cmt.

2.1.6 arch/arm/mach-spear/

PLAT_SPEAR boards do not use sh_cmt.

  1. arch/arm/mach-spear/spear13xx.c:122
    clk_set_parent(gpt_clk, pclk);
    
  2. arch/arm/mach-spear/spear3xx.c:111
    clk_set_parent(gpt_clk, pclk);
    
  3. arch/arm/mach-spear/spear6xx.c:398
    clk_set_parent(gpt_clk, pclk);
    

2.1.7 arch/arm/plat-omap/

ARCH_OMAP boards do not use sh_cmt.

  1. arch/arm/plat-omap/dmtimer.c:157
    ret = clk_set_parent(timer->fclk, parent);
    
  2. arch/arm/plat-omap/dmtimer.c:563
    ret = clk_set_parent(timer->fclk, parent);
    

2.2 arch/sh

2.2.1 arch/sh/boards/board-apsh4a3a.c:131

ret = clk_set_rate(clk, 33333000);

2.2.2 arch/sh/boards/board-apsh4ad0a.c:109

ret = clk_set_rate(clk, 33333000);

2.2.3 arch/sh/boards/board-sh7785lcr.c:306

ret = clk_set_rate(clk, 33333333);

2.2.4 arch/sh/boards/board-urquell.c:196

ret = clk_set_rate(clk, 33333333);

2.2.5 arch/sh/boards/mach-ecovec24/

SH_ECOVEC depends on CPU_SUBTYPE_SH7724 and thus, does use the sh_cmt device.

  1. arch/sh/boards/mach-ecovec24/setup.c:1359
    clk_set_rate(clk, clk_round_rate(clk, 83333333));
    

    clk is spu_clk which is equivalent to &div6_clks[DIV6_S]. This isn't a member of the sh_cmt clock tree on CPU_SUBTYPE_SH7724.

  2. arch/sh/boards/mach-ecovec24/setup.c:1367
    clk_set_rate(&sh7724_fsimckb_clk, 48000);
    

    sh7724_fsimckb_clk isn't a member of the sh_cmt clock tree on CPU_SUBTYPE_SH7724.

  3. arch/sh/boards/mach-ecovec24/setup.c:1368
    clk_set_parent(clk, &sh7724_fsimckb_clk);
    clk_set_rate(clk, 48000);
    

    clk is fsib_clk which is equivalent to &div6_clks[DIV6_FB]. This isn't a member of the sh_cmt clock tree on CPU_SUBTYPE_SH7724.

  4. arch/sh/boards/mach-ecovec24/setup.c:1384
    clk_set_rate(clk, clk_round_rate(clk, 166000000));
    

    clk is vpu_clk which is equivalent to &div4_clks[DIV4_M1]. This isn't a member of the sh_cmt clock tree on CPU_SUBTYPE_SH7724.

2.2.6 arch/sh/boards/mach-kfr2r09/setup.c:286

ret = clk_set_rate(camera_clk, rate);

SH_KFR2R09 depends on CPU_SUBTYPE_SH7724 and thus, does use the sh_cmt device.

However, camera_clk is video_clk which is equivalent to &div6_clks[DIV6_V]. This isn't a member of the sh_cmt clock tree on CPU_SUBTYPE_SH7724.

2.2.7 arch/sh/boards/mach-migor/setup.c:315

clk_set_rate(camera_clk, 10000000);

SH_MIGOR depends on CPU_SUBTYPE_SH7722 and thus, does use the sh_cmt device.

However, camera_clk is video_clk which is equivalent to &div6_clks[DIV6_V]. This isn't a member of the sh_cmt clock tree on CPU_SUBTYPE_SH7722.

2.2.8 arch/sh/boards/mach-sdk7786/setup.c:207

ret = clk_set_rate(clk, 33333333);

2.2.9 arch/sh/boards/mach-se/7724/

SH_7724_SOLUTION_ENGINE depends on CPU_SUBTYPE_SH7724 and thus, does use the sh_cmt device.

  1. arch/sh/boards/mach-se/7724/setup.c:844
    clk_set_rate(clk, clk_round_rate(clk, 83333333));
    

    clk is spu_clk which is equivalent to &div6_clks[DIV6_S]. This isn't a member of the sh_cmt clock tree on CPU_SUBTYPE_SH7724.

  2. arch/sh/boards/mach-se/7724/setup.c:852
    clk_set_rate(&sh7724_fsimcka_clk, 48000);
    

    sh7724_fsimcka_clk isn't a member of the sh_cmt clock tree on CPU_SUBTYPE_SH7724.

  3. arch/sh/boards/mach-se/7724/setup.c:853
    clk_set_parent(clk, &sh7724_fsimcka_clk);
    clk_set_rate(clk, 48000);
    

    clk is fsia_clk which is equivalent to &div6_clks[DIV6_FA]. This isn't a member of the sh_cmt clock tree on CPU_SUBTYPE_SH7724.

Author: Nicolai Stange

Created: 2017-02-05 Sun 15:30

Emacs 25.1.1 (Org mode 8.2.10)

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